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VHDL Coding for Synthesis
Advanced Level.   4 Days:   50% Lecture, 50% Labs

Course Overview
An in-depth study of VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic.

Class topics focus on mapping digital hardware structures to vendor independent VHDL code. Detailed do's and don'ts of synthesis coding styles are discussed. Lecture and laboratory materials illustrate the optimization differences achieved by different VHDL coding styles. Students will learn proven coding practices that result in smaller and faster designs. The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.

Intended Audience
The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.

Available Class Formats
This class is available online, at public venues, or on-site (at your location).

Course Objectives
Upon completion of this course, students will be able to:
  • Write efficient, vendor independent VHDL code
  • Use best coding styles and practices to create ASIC and FPGA logic
  • Understand and avoid problematic hardware coding styles
  • Use code templates to create a design from the block diagram
  • Read VHDL code and draw the corresponding hardware (reverse engineer)
  • Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164, numeric_std, and std_logic_arith)
  • Use advanced VHDL constructs to simplify the coding process
  • Identify and solve synthesis issues using VHDL coding techniques
  • Force a synthesis tool to create the desired logic structure

Course Outline
      Day 1, Module Syn1
Synthesis Overview
Combinational Logic
Registers and Latches
UART Transmitter: RTL Code + Statemachine

      Day 3, Module AdvSyn1
Subprograms for Synthesis
Advanced Combinational Logic
Advanced Sequential Logic
Parameterizing Designs

      Day 2, Module Syn2
Numeric Types and Packages
Arithmetic Logic
Comparison and Multiplication
Partitioning
Synthesis Process

      Day 4, Module AdvSyn2
Advanced Arithmetic
Architecting Hardware
TxPort Statemachine
Fixed and Floating Point Types

Prerequisites
Students taking this course should have working knowledge of digital circuits and prior exposure to VHDL through experience or the course:
Other Recommended Courses
Students may also be interested in the following companion course:
Customization
Students taking this course should have working knowledge of digital circuits and prior exposure to VHDL through experience or the course:
Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.


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