SynthWorks Expert VHDL Training for Hardware Design and Verification
Comprehensive VHDL Intro
(4 Days)

Adv VHDL Testbenches & Verification
(5 Days)

VHDL Synthesis (4 Days)
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SynthWorks Training
Jumpstart your VHDL design and verification tasks
SynthWorks provides VHDL training that improves the productivity and effectiveness with which FPGA and ASIC design and verification engineers complete their projects.   We offer introductory VHDL classes as well as advanced classes for VHDL based design and verification (testbenches).

Online, Instructor-Led Classes
In addition to on-site and public venue classes, we also offer online VHDL classes.   We have been doing this for over 7 years now - so we are good at it.   Our instructor-led online classes cover the same material as we do in a classroom session.   Lecture and labs are provided in half day sessions allowing training to be mixed with work responsibilities.   Use phone or integrated audio (via your computer) to listen and ask questions.   No travel required, attend from your desk or home.  
Online class details.     Online class schedule.

Get VHDL hardware experience with our FPGA lab board.

Learn from leaders in IEEE VHDL Standards and OSVVM.
Our instructors are VHDL design and verification experts as well as leaders in IEEE VHDL standards and open source VHDL projects, such as the Open Source VHDL Verification Methodology (OSVVM).   Our principal instructor co-authored the book: VHDL 2008: Just the New Stuff .   SynthWorks co-founded OSVVM with Aldec and is the chief architect of the packages and methodology.   Your business is essential to our supporting these efforts.

Learn Leading-Edge, Best-Coding Practices
We have been teaching best VHDL coding practices since 1997.   Our classes are kept under a continual refinement process to ensure you get the latest information.   We believe our classes are the best in the industry and back them with a satisfaction guarantee.  

VHDL verification is our specialty
SynthWorks is the brains behind the Open Source VHDL Verification Methodology (OSVVM). OSVVM is the #1 VHDL Verification Methodology. (world wide) ASIC level VHDL verification methodology that provides the same capabilities and benefits as other verification languages (such as SystemVerilog and UVM), yet is simple enough to use on small FPGA projects. Our Advanced VHDL Testbenches and Verification class is an effective Boot Camp for learning OSVVM.  

Jumpstart your verification effort by using the OSVVM library for constrained random and Intelligent Coverage™ Random testing, functional coverage, Error logging and reporting, scoreboards, transaction based modeling, and memories.

Learn from Our VHDL Experts
Our instructors have solved difficult design and verification coding problems and can answer your questions in detail.

Vendor independent training
Learn using the tools and FPGA of your choice.   While we have close ties with EDA vendors and teach how to use their tools, we also focus on teaching vendor independent VHDL coding techniques.   Learn coding styles that are portable and effective for all EDA tools.  

VHDL Training Course Summary

Comprehensive VHDL Introduction   - 4 Day - Beginners Class
Learn VHDL for FPGA and ASIC design and verification.   Class covers syntax, RTL coding, and testbenches.   Class comes with your choice of an Altera or Xilinx FPGA board to make sure you understand the whole process from simulation to chip
Advanced VHDL Testbenches and Verification   - 5 Days
Learn the latest VHDL verification techniques including transaction based modeling (aka verification components), self-checking, error reporting (alerts and affirmations), message filtering (logs), scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and Intelligent Coverage random test generation. Create an OSVVM VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or 'e'. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.
VHDL Coding for Synthesis   - 4 Days
Learn VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic.
Customization Your On-site Class
Our classes are modular and customizable.   Need something special in your on-site class?   Whether it is a custom focus or class length, we can do it.   Contact us for details.