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Day 1, Synthesis Module AdvSyn1
Subprograms for Synthesis
Advanced Combinational Logic
Advanced Sequential Logic
Parameterizing Designs
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Day 3, Testbench Module Tb1
Lab Review: UartTx BFM
Creating Tests
Constrained Random Testing
Functional Coverage
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Day 2, Synthesis Module AdvSyn2
Advanced Arithmetic
Architecting Hardware
TxPort Statemachine
Fixed and Floating Point Types
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Day 4, Testbench Module Tb2
Execution and Timing
Configurations and Simulation Management
Advanced Coverage
Advanced Randomization
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Day 5, Testbench Module Tb3
Lab Review: Scoreboards, Randomization, and Coverage
Modeling RAM
Test Plans
Transaction-Based BFM, Part 2
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