Synthworks' Advanced VHDL for Synthesis and Verification


Schedule
Courses
	Comprehensive VHDL Intro (4 Days)
	Adv VHDL Testbenches & Verification (5 Days)
	VHDL Synthesis (4 Days)

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Advanced VHDL for Synthesis and Verification
Advanced Level. 3-5 Days: 50% Lecture, 50% Labs

Course Overview
This is a custom class in which course materials are selected from the following core courses:

Advanced VHDL Coding for Synthesis (2 days)
Advanced VHDL Testbenches and Verification (5 days)

Course Outline A full 5 day course is as follows

	Day 1, Synthesis Module AdvSyn1 Subprograms for Synthesis Advanced Combinational Logic Advanced Sequential Logic Parameterizing Designs		Day 3, Testbench Module Tb1 Lab Review: UartTx BFM Creating Tests Constrained Random Testing Functional Coverage
	Day 2, Synthesis Module AdvSyn2 Advanced Arithmetic Architecting Hardware TxPort Statemachine Fixed and Floating Point Types		Day 4, Testbench Module Tb2 Execution and Timing Configurations and Simulation Management Advanced Coverage Advanced Randomization
			Day 5, Testbench Module Tb3 Lab Review: Scoreboards, Randomization, and Coverage Modeling RAM Test Plans Transaction-Based BFM, Part 2

Customization Possibilities

5 Day Class: AdvSyn1, AdvSyn2, Tb2, Tb3, Tb4
4 Day Class: AdvSyn1, AdvSyn2, Tb1, Tb2
3 Day Class: AdvSyn1, AdvSyn2, Tb1
4 Day Class: AdvSyn1, AdvSyn2, Tb3, Tb4 – only if previously took Tb2

Note it is also possible to include materials from the Intermediate VHDL Coding for Synthesis class.

Prerequisites
Students taking this course should have significant experience designing and testing digital logic with VHDL or have taken the course:

Intermediate VHDL for Synthesis and Verification - 3-5 days

Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.