An in-depth study of advanced VHDL techniques for FPGA and ASIC design engineers.
Class topics focus on coding techniques, advanced language features (subprograms, generics, generate, packages), issue identification and problem solving. Lecture sections contain short exercises for immediate learning feedback. Labs, which account for approximately 50% of class time, give students the opportunity to experiment with different coding styles and problem solving techniques using the synthesis tool.
All of our courses can be customized to meet your specific needs.
For some ideas, see customized courses.
This hands-on, how-to course is taught by experienced hardware designers using a computer
driven projector. We prefer and encourage student and instructor interaction.
Questions are welcome. Bring problematic code.