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VHDL Synthesis (4 Days)

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Intermediate VHDL for Synthesis and Verification
Intermediate Level. 4 Days: 50% Lecture, 50% Labs

Course Overview
Course materials come from the following core courses:
  • Intermediate VHDL Coding for Synthesis (2 days)
  • Advanced VHDL Testbenches and Verification (5 days)

Course Outline A full 5 day course is as follows
      Day 1, Synthesis Module Syn1
Synthesis Overview
Combinational Logic
Registers and Latches
UART Transmitter: RTL Code + Statemachine

      Day 3, Testbench Module Tb1
Testbench Overview
Basic Testbenches
Transactions and Subprograms
Modeling for Verification

      Day 2, Synthesis Module Syn2
Numeric Types and Packages
Arithmetic Logic
Comparison and Multiplication
Synthesis Process

      Day 4, Testbench Module Tb2
Lab Review: Testing w/ subprograms
Transaction-Based Models (BFM)
Elements of a Transaction-Based BFM
Data Structures for Verification

              Day 5, Testbench Module Tb3
Creating Tests
Constrained Random Testing
Functional Coverage

Customization Possibilities
  • 4 Day Class: Syn1, Syn2, Tb1, Tb2
  • 4 Day Class: Syn1, Syn2, Tb1, Tb2
  • 3 Day Class: Syn1, Syn2, Tb1
Note it is also possible to include materials from the Advanced VHDL Coding for Synthesis class.

Intended Audience
The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.

Students taking this course should have working knowledge of digital circuits and prior exposure to VHDL through experience or the course: Follow-On Courses
Students wishing to go beyond what they learned in this course should take:
Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.

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