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Jim Lewis
ASIC and FPGA Design and Verification

Jim Lewis Phone: 503-590-4787      Contract Status      Email:

Services Offered
  • VHDL Training
  • Open Source VHDL Verification Methodology (OSVVM) Model Development
  • Design Verification planning and implementation
  • ASIC and FPGA design
  • Design process automation
  • VHDL code and methodology review
Background
Experienced team leader, designer, trainer, and problem solver in ASIC and FPGA design and verification.

Career Highlights
  • IEEE 1076 VHDL Working Group Chair
  • Developed Open Source VHDL Verification Methodology (OSVVM), the #1 VHDL FPGA Verification Methodology
  • Team member, problem solver, and Trainer (VHDL simulation, synthesis, and methodology) for Lockheed Sanders in their development of 22 ASICs for the F22 program.
  • Team member, problem solver, and Trainer (Synopsys synthesis scripts and VHDL synthesis) for SGS Thomson in their development of a Video Codec.
  • VHDL ASIC design (at Intel, Lockheed, SGS Thomson).
  • VHDL FPGA design (Altera, Actel, and Xilinx)
  • Lead designer of a 24K gate DMA Controller ASIC for TRW's Milstar satellite program (with scan).
  • Team member of TRW's VHDL methodology development group
  • Experienced with planning and recovery strategies for VHDL based design.
Tool and Vendor Experience
  • Mentor QuestaSim/ModelSim simulation tools
  • Aldec RiveriaPro and ActiveHDL simulation tools
  • Synopys Synplify and Design Compiler synthesis tools
  • Synopys VSS VHDL Simulator
  • Altera, Actel, and Xilinx FPGA design tools
  • Exemplar synthesis tools
  • OKI, TI, SGS-Thomson, Honeywell ASIC Libraries
Education
      MSEE Purdue University May 1986 3.85/4.0 GPA
      BSCEE Purdue University Dec 1984 3.95/4.0 GPA

Detailed Work Experience
Director of Training, SynthWorks Design Inc. (1997 - Current)
Responsible for all aspects of the VHDL training business.

Architect and Principal Developer, Open Source VHDL Verification Methodology (OSVVM) (2012 - Current)
Responsible for all aspects of OSVVM, the #1 VHDL Verification Methodology. The OSVVM utility library provides similar capabilities to other verification languages, such as SystemVerilog + UVM. OSVVM capabilities include transaction level modeling, error handling and conditional messaging (debug messages+), functional coverage, constrained random and Intelligent Coverage Random test generation, data structures (scoreboards, ...), and basic utilities (synchronization, clock generation, ...). The OSVVM model library provides common models such as Axi4Lite, AxiStream, and UART. The intention of OSVVM goes beyond being simple and powerful — OSVVM makes verification environments easy, readable, and fun.

Chair, IEEE P1076 VHDL Analysis and Standards Group (VASG). (2007 - Current)
Working group chair for IEEE VHDL Standards Group.

Consultant, ASIC and FPGA Design and Synthesis (1994 - Current)
VHDL based ASIC and FPGA design, simulation and synthesis.

Supported Orbital's development of OSVVM testbench models.

Supported Kentrox's IMA ATM board development. Designed components in the ATM data path. Targeted Altera 10K50 FPGA devices.

Supported Intel's Netport product, a network print server. Designed ASIC which included Intel 486 interface, DRAM, DMA controller, and IEEE 1284 Parallel Ports.

Zycad, Protocol Senior Systems Engineer (Nov 92 - July 94)
On-site consulting in VHDL methodologies for ASIC design and system simulation.

Team member, trainer, and methodology consultant for Lockheed Sanders in their development of 22 ASICs for the F22 program. Gave training in VHDL synthesis and simulation. Designed an ASIC. Assisted with directory and library organization, development of multiple ASIC simulations, and development of reusable testbench models.

Team member, trainer, and VHDL consultant for SGS Thomson in their development of a Video Codec. Gave training in VHDL coding for synthesis and synthesis strategies with Synopsys tools. Designed, simulated, and synthesized several pieces of the ASIC. Became a site focal point for VHDL synthesis issues.

TRW Senior MTS (Aug 86 - Nov 92)
Team member of R3000 computer system design. Developed the system bus for connecting the Data Processor with main memory and IO devices. Designed the Bus Controller and Memory Controller FPGAs using VHDL and Synopsys simulation and synthesis tools. Developed the testbench for multiple chip simulations. Wrote Unix scripts to convert from VHDL Textio format to Rapidsim tabular trace files and to automate the process from synthesis to producing a routed Actel design. Coordinated board test.

Team member of TRW's VHDL methodology development group.

Lead designer of a Direct Memory Access (DMA) Controller Gate Array for a Mil-Std-1750A Computer. Developed the chip specification. Led a team of engineers through design, simulation, and test vector generation. Used ETM scan methodology to increase testability of the chip. Wrote C programs and UNIX scripts to automate our design process.

Developed a 400 MByte/sec I/O system for a vector processor implemented using TRW's wafer scale technology. Used functional redundancy and Built in Self Test (BIST) to increase the yield of chips with a large die size.

Purdue University Teaching Assistant (Jan 85 - May 86)
Taught two sections of a microprocessor laboratory course.

TRW Cleveland Coop Engineer (Aug 81 - Aug-84)*
Designed an image capture system for a digital camera. Responsible for board design and debug, system integration, and software development.

     * Dates are alternating with school.

Outside Interests
Active in skiing, kayaking, and Ultimate Frisbee.

To view Mr. Lewis' biography, click here.
For information about Mr. Lewis' consulting services, click here.



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