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VHDL Course Overview
Whether you are just getting started or looking to improve your
verification or synthesis coding techniques, SynthWorks has a class
for you.
Comprehensive VHDL Introduction - 4 Days
Basic Level, 50% Lecture, 50% Labs
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An in-depth introduction to VHDL and its application to design and verification of digital hardware (FPGAs and ASICs). Students will gain a strong foundation in VHDL RTL and testbench coding techniques. Lectures contain numerous examples that show both syntax and coding style guidelines. Labs give students hands-on experience writing RTL code, writing testbenches, running your simulator and synthesis tools, and programming our FPGA based lab board. Recommended as a first course for design and verification engineers who need a solid foundation in VHDL.
Get VHDL hardware experience with our FPGA based lab board.
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Advanced VHDL Testbenches and Verification - 5 Days
Advanced Level, 50% Lecture, 50% Labs
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An in-depth study of advanced VHDL Verification techniques and methodologies for FPGAs, PLDs, and ASICs, including the Open Source VHDL Verification Methodology (OSVVM). This course starts with simple testbenches and progressively increases the level of abstraction. Along the way students learn about subprogram usage, libraries, file reading and writing, error reporting (Alerts and Affirmations), message handling (logs), transaction-based testbenches, bus functional models, abstractions for interface connectivity, model synchronization methods, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage driven random test generation, self-checking (result, timing, protocol checking and error injection), functional coverage, representation of analog values and periodic waveforms, timing and execution of code, configurations, test planning, and reuse. The final result is a system-level, transaction-based, self-checking test environment. Labs track with lecture giving students the opportunity to apply what they learn.
Jumpstart your verification effort by reusing OSVVM packages for
transaction based modeling,
constrained and Intelligent Coverage™ random testing,
functional coverage,
error and message handling,
interprocess synchronization,
scoreboards, FIFOs, and memories
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VHDL Coding for Synthesis - 4 Days
Advanced Level, 50% Lecture, 50% Labs
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An in-depth study of VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic. Class topics focus on mapping digital hardware structures to vendor independent VHDL code. Detailed do's and don'ts of synthesis coding styles are discussed. Lecture and laboratory materials illustrate the optimization differences achieved by different VHDL coding styles. Students will learn proven coding practices that result in smaller and faster designs. The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.
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Customized VHDL Training Classes
Tailor-Fit the Training You Need...
Our class offerings are modular and flexible and can be
customized to meet the needs of your team.
This could include shortening an existing class,
combining materials from one or more classes, or
consulting in one of the following areas:
- FPGA or ASIC design or verification project jumpstart
- FPGA or ASIC design or verification project services
- Hardware System Architecture
- Design Automation
The following table will give you some ideas to possible class customizations.
If you do not find what you are looking for, contact us and we will customize
a class for you.
VHDL Introduction for Verilog Designers - 1-4 Days
Basic Level
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Due to the differences in Verilog and VHDL, generally we recommend
taking the entire Comprehensive VHDL Introduction.
However, we are happy to adapt the course to any length you like.
After taking one of our courses, the most frequent comment we
get from Verilog coders is,
"I thougth VHDL was supposed to be hard if you had learned Verilog first."
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Intermediate VHDL Coding for Synthesis - 2 Days
Intermediate Level, 50% Lecture, 50% Labs
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An in-depth study of VHDL coding styles, methodologies, and design techniques used to efficiently synthesize digital hardware (ASICs and FPGAs). Class topics focus on mapping digital hardware structures to vendor independent VHDL code. Detailed do's and don'ts of synthesis coding styles are discussed. Lecture and laboratory materials illustrate the optimization differences achieved by different VHDL coding styles. Students will learn proven coding practices that result in smaller and faster designs. The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.
This class is the first half of
VHDL Coding for Synthesis
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Advanced VHDL Coding for Synthesis - 2 Days
Advanced Level, 50% Lecture, 50% Labs
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An in-depth study of advanced VHDL RTL coding techniques for FPGA and ASIC design engineers. Class topics focus on coding techniques, advanced language features (subprograms, generics, generate, packages), issue identification and problem solving. Lecture sections contain short exercises for immediate learning feedback. Labs, which account for approximately 50% of class time, give students the opportunity to experiment with different coding styles and problem solving techniques using the synthesis tool.
This class is the second half of
VHDL Coding for Synthesis
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Intermediate VHDL for Synthesis and Verification - 3-5 Days
Intermediate Level, 50% Lecture, 50% Labs
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Covers both testbench and intermediate RTL coding topics. Covers selected topics from Intermediate VHDL Coding for Synthesis and the Advanced VHDL Testbenches and Verification class.
In a public venue, we offer these courses on the same week and allow students to sign?up for each separately. For on-site classes, it is possible to shorten either the synthesis or verification portion of the class.
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Advanced VHDL for Synthesis and Verification - 3-5 Days
Advanced Level, 50% Lecture, 50% Labs
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Covers both testbench and advanced RTL coding topics. Covers selected topics from Advanced VHDL Coding for Synthesis and the Advanced VHDL Testbenches and Verification class.
In a public venue, we offer these courses on the same week and allow students to sign?up for each separately. For on-site classes, it is possible to shorten either the synthesis or verification portion of the class.
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Quick VHDL Introduction - 2 Days
Basic Level, 60% Lecture, 40% Labs
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Comprehensive VHDL Introduction shortened for support engineers and managers who only need to understand the basics of using VHDL in a design environment. Only recommended for design and verification engineers when they plan on immediately following it with additional training.
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