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Comprehensive VHDL Intro
(4 Days)

Adv VHDL Testbenches & Verification
(5 Days)

VHDL Synthesis (4 Days)

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Quick VHDL Introduction
Basic Level. 2 Days: 60% Lecture, 40% Labs

Course Overview
Comprehensive VHDL Introduction shortened for support engineers and managers who only need to understand the basics of using VHDL in a design environment. Only recommended for design and verification engineers when they plan on immediately following it with additional training.

Through two days of lecture, exercises, and labs, students will learn basic VHDL coding and simulation techniques. Lectures contain examples that show both syntax and coding style guidelines. Exercises provide immediate reinforcement of lecture materials. Labs give students hands-on experience writing VHDL code and running your simulator.

Course Objectives
Upon completion of this course, students will be able to:
  • Understand VHDL keywords, syntax and coding styles necessary for logic design
  • Write simple VHDL models, netlists, and testbenches
  • Read and understand more complex VHDL models
Course Outline
      Day 1
A Quick Introduction
Lab 1: Simple RTL and Testbench
Data Types
Concurrent Statements
Sequential Statements
Lab 2: Clock and Reset
Lab 3: RTL and Testbench

      Day 2
Statemachine Coding Techniques
Lab4: RTL Code
Data Objects
Designing with VHDL
Lab 5: Coding an FSM
Lab 6: Creating Hierarchy

None. Offered as a first course in VHDL. It is recommended that students are familiar with digital design and know how to use the editors and operating system used in the labs.

Follow-On Courses
Students wishing to go beyond what they learned in this course should take either or both of the following courses: Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.

All of SynthWorks' courses can be customized to meet your specific needs.

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