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Day 1, Module Syn1
Synthesis Overview
Combinational Logic
Registers and Latches
UART Transmitter: RTL Code + Statemachine
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Day 3, Module AdvSyn1
Subprograms for Synthesis
Advanced Combinational Logic
Advanced Sequential Logic
Parameterizing Designs
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Day 2, Module Syn2
Numeric Types and Packages
Arithmetic Logic
Comparison and Multiplication
Partitioning
Synthesis Process
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Day 4, Module AdvSyn2
Advanced Arithmetic
Architecting Hardware
TxPort Statemachine
Fixed and Floating Point Types
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